High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators

Multiplication is one of the widely used arithmetic operations in a variety applications, such as image/video processing and machine learning. FPGA vendors provide high-performance multipliers form DSP blocks. These are not only limited number have fixed locations on FPGAs but can also create additional routing delays may prove inefficient for smaller bit-width multiplications. Therefore, additionally optimized soft IP cores multiplication. However, this work, we advocate that these multiplier still need better designs to resource efficiency. Toward this, present generic area-optimized, low-latency accurate, approximate softcore architectures, which exploit underlying architectural features FPGAs, i.e., lookup table (LUT) structures fast-carry chains reduce overall critical path delay (CPD) utilization multipliers. Compared Xilinx LogiCORE IP, our proposed unsigned signed accurate architecture provides up 25% 53% reduction LUT utilization, respectively, different sizes Moreover, with 51% CPD be achieved an insignificant loss output accuracy when compared IP. For illustration, deployed accelerators image video evaluated them area performance gains. Our library opensource available online at https://cfaed.tu-dresden.de/pd-downloads fuel further research development area, facilitate reproducible research, thereby enabling new direction community.